1. Field of the Invention
The present invention relates to a test method for effectively performing a test on a semiconductor memory which requires rewriting of data or a semiconductor memory which is provided with some error memory cells but regarded as acceptable since the number of normal memory cells is not less than a predetermined number (hereinafter referred to as xe2x80x9cMGM (Mostly Good Memory)xe2x80x9d). The present invention also relates to an semiconductor test apparatus which comprises circuits for the above test method.
2. Description of the Background Art
 less than Characteristics of Flash Memory greater than 
A flash memory is one of so-called nonvolatile memories which hold stored data even if power is lost. It is capable of electrically erasing the stored data.
The flash memory stores either xe2x80x9c0xe2x80x9d or xe2x80x9c1xe2x80x9d in each memory cell by varying the threshold values of those cells. Erasing such data is performed not by one erase operation but by repetitions of the operation to gradually lower the threshold value. Since there is a restriction on the number of times the erase operation can be repeated (hereinafter referred to as xe2x80x9cthe number of retriesxe2x80x9d), it is necessary in the erase test to check whether all cells have been erased within a predetermined limitation of times or not. The principle and operating mechanism of an NOR type flash memory are, for example, disclosed in Mitsubishi Semiconductor Data Book 1997, Mitsubishi Application Note, p4-8-p4-15 issued by the semiconductor business planning department of Mitsubishi Electric Corporation (prior art reference (1)).
To erase data stored in the NOR type flash memory, a method for erasing data by one operation is employed. This is not to erase data of a specific cell but to erase all cells in the memory. Thus, it is necessary not only to check at each address of the memory whether the erasing has been completed or not, but also to check the total number of erase retries during test irrespective of the addresses. The procedure (hereinafter referred to as xe2x80x9ctest flowxe2x80x9d) of the erase test is, for example, disclosed in Mitsubishi Semiconductor Data Book 1997, Mitsubishi Application Note, p4-18, 19 (prior art reference (2)). Similarly, a write test flow is disclosed in Mitsubishi Semiconductor Data Book 1997, Mitsubishi Application Note, p4-16, 17 (prior art reference (3)).
 less than Conventional Test Apparatus and Method greater than 
Conventional circuitry for the flash memory test is approximately configured as shown in FIGS. 34 and 35, which includes a test pattern generating portion and a controller portion for controlling write and erase retry operations. In the structure of FIGS. 34 and 35, there are two memories under test 8 (8a, 8b). FIG. 47 shows connection between FIGS. 34 and 35.
A semiconductor test apparatus comprises a clock generator 6 for generating a periodic clock signal 1 which is test periodic timing, a synchronizing clock signal 2 for synchronization with signals, a delay clock signal 3 for delaying signals, an event clock signal 4 which is timing of test pattern changes, and a strobe signal 5 which is judgement timing; an instruction memory 7 for storing a program which describes test patterns generated during operation; and an address generator 10 for decoding the program from the instruction memory 7 and generating address patterns 9 (9a, 9b) to have access to the memories under test 8 (8a, 8b).
The semiconductor test apparatus further comprises a data generator 14 for decoding the program from the instruction memory 7 and generating data patterns 11 (11a, 11b) to be applied to the memories under test 8 and data patterns 13 (13a, 13b) to be compared with data 12 (12a, 12b) from the memories under test 8; control signal generators 16 (16a, 16b) for generating control patterns 15 (15a, 15b) to be applied to the memories under test 8; and a program counter 18 for generating an address 17 to have access to the instruction memory 7.
In addition, the semiconductor test apparatus comprises signal waveform forming circuits 20 (20a, 20b) for generating input signals 19 (19a, 19b) to be applied to the memories under test 8 with timings of the event clock signal 4 from the clock generator 6 and various patterns from the address generator 10; the data generator 14; and the control signal generators 16 (16a, 16b).
The test apparatus is further provided with judging circuits 25 for comparing the output data 12 from the memories under test 8 with the data patterns 13 from the data generator 14 with timing of the strobe signal 5 from the clock generator 6, applying error signals 21 (21a, 21b) and 22 (22a, 22b), or comparison result, to a match controller portion 23P, and canceling the error signals 21, 22 on receipt of reset signals 24 (24a, 24b) from the match controller portion 23P. On receipt of a match control signal 26 from the instruction memory 7, the match controller portion 23P performs retry operations in synchronization with the clocks signals 1, 2. Signals 27 through 31 will be described later with reference to FIGS. 36 and 37.
FIGS. 36 and 37 show the circuit configuration of the match controller portion 23P. As a matter of convenience, some of external input signals in FIGS. 36 and 37 are not shown in FIGS. 34 and 35, but they exist in practice. FIG. 48 shows connection between FIGS. 36 and 37.
A periodic delay circuit 33 in the match controller portion 23P is composed of a D flip-flop 501 and an AND gate 502. It generates a control delay clock signal 32 by delaying the match control signal 26 for a single one period by the periodic clock signal 1 as shown in FIG. 41. A pipeline circuit 34 receives the output signal 32 of the periodic delay circuit 33 and outputs a signal 35, which is delayed with the synchronizing clock signal 2 as a trigger, to one input of an AND gate 503. Receiving the synchronizing clock signal 2 at its other input, the AND gate 503 outputs a signal 36 which is pulse-converted by the synchronizing clock signal 2. For reference, a correlation between the control delay clock signal 32 and the signal 36 is shown in FIG. 42. The match controller portion 23P operates in synchronization with this signal 36, so that match control by the match controller portion 23P is enabled after a delay of a single period.
A clock stop latch circuit 45 (45a, 45b) receives at its set input S the output of an AND gate 508 (508a, 508b) which receives the error signal 21(21a, 21b) and the signal 36. If the error signal 21 is xe2x80x9c1 (pass)xe2x80x9d, the circuit 45 sets a temporary clock stop signal 37 (37a, 37b) to xe2x80x9c1xe2x80x9d and a signal 38 (38a, 38b), which is to be a switching signal 27 for the execution address 17 indicated by the program counter 18, to xe2x80x9c0xe2x80x9d
The clock stop latch circuit 45 further receives at its reset input R an output signal 44 (44a, 44b) of an AND gate 507. If a signal 39 and the match control signal 26 are both xe2x80x9c1xe2x80x9d, a periodic delay circuit 40 (composed of an AND gate 504, a D flip-flop 505, and an AND gate 506) outputs a control delay clock signal 41 which is xe2x80x9c1xe2x80x9d in synchronization with the periodic clock signal 1. A signal 43 obtained by delaying the control delay clock signal 41 in a pipeline circuit 42 is given to one input of the AND gate 507. Since the AND gate 507 receives at its other input the synchronizing clock signal 2, the signal 43 is pulse-converted by the synchronizing clock signal 2 to be the reset signal 44 (44a, 44b). By this reset signal 44, the clock stop latch circuit 45 cancels a temporary clock stop condition.
A loop counter 49 (49a, 49b) increments the number of retries with the output of an AND gate 510 (510a, 510b) as a synchronizing signal. The AND gate 510 receives the signal 36 and a signal obtained from the error signal 21 through an inverter 509. A register circuit 46, on the other hand, holds a limited number of retries 29 from the instruction memory 7 in synchronization with the periodic clock signal 1.
If the error signal 21 is xe2x80x9c0 (fail)xe2x80x9d, the loop counter 49 increments the number of retries in synchronization with the signal 36. If the count agrees with an output value 47 of the register circuit 46, an counter error signal 48 (48a, 48b) is set to xe2x80x9c1xe2x80x9d.
If the counter error signal 48 is xe2x80x9c1xe2x80x9d, an error latch circuit 52 (52a, 52b) which receives the signal 48 at its set input S sets a clock stop signal 50 (50a, 50b) to xe2x80x9c1xe2x80x9d and a signal 51 (51a, 51b), which is to be the switching signal 27 for the execution address 17, to xe2x80x9c0xe2x80x9d.
An AND gate 520 (520a, 520b) inputs the signals 50 (50a, 50b), 36 and outputs the reset signal 24 (24a, 24b). An inverter 521 outputs the signal 39 which is obtained by inverting the execution address switching signal 27.
Accordingly, if the signal 50 is xe2x80x9c0xe2x80x9d and the signal 36 is xe2x80x9c1xe2x80x9d, the error signal 21 held in the judging circuit 25 (cf. FIGS. 34, 35) is reset since the reset signal 24 (24a, 24b) becomes xe2x80x9c1xe2x80x9d. If the signal 50 is xe2x80x9c1xe2x80x9d, the reset is disabled since the reset signal 24 becomes xe2x80x9c0xe2x80x9d.
The output of an OR gate 511 (511a, 511b) which receives the signals 37 and 50 becomes a clock stop signal 30 (30a, 30n), and the output of an OR gate 512 (512a, 512b) which receives the signals 38 and 51 becomes a signal 53 (53a, 53b). Then, the output of an OR gate 513 which receives the outputs of the OR gates 512a, 512b becomes the execution address switching signal 27.
Thus, if the signals 53 of all memories under test are xe2x80x9c0xe2x80x9d (i.e., signals 38 and 51 are both xe2x80x9c0xe2x80x9d), the execution address switching signal 27 is asserted (=xe2x80x9c0xe2x80x9d). It performs switching between the address from the program counter 18 and an address 28 from the instruction memory 7 under control of the mach control signal 26.
The (temporary) clock stop signal 30 is a signal to disable the generation of the input signal 19 and the judging operation of the judging circuit 25. This signal 30 is asserted (=xe2x80x9c1xe2x80x9d) when either the signal 37 or the signal 50 is xe2x80x9c1xe2x80x9d. xe2x80x9cTemporary clock stopxe2x80x9d means that in simultaneous tests on a plurality of flash memories, for example, the generation of the input signals and the operation of the judging circuit for a memory under test which has passed during the retry operation are temporarily disabled until the retry operations for the other memories under test are completed. xe2x80x9cClock stopxe2x80x9d means that the generation of the input signals and the operation of the judging circuit for a memory under test which exceeds the limited number of retries are completely disabled until the end of the test. A (temporary) clock stop function includes a function to disable all signals of each memory under test or a function to disable a specific control signal.
A signal 31 includes a test stop seizing signal 31a and a stop signal 31b. An AND gate 514 inputs the test stop seizing signal 31a and the periodic clock signal 1, whereas an AND gate 515 inputs the stop signal 31b and the periodic clock signal 1. The outputs of the AND gates 514 and 515 enter at the set input S and reset input R of a status holding circuit (RS flip-flop) 55, respectively. A Q-output signal 56 of the status holding circuit 55 becomes a signal 58 via a pipeline circuit 57 using the synchronizing clock signal 2 as a synchronizing signal, and enters at one input of an AND gate 519.
An AND gate 516 inputs the signals 50a and 50b, whereas an AND gate 517 inputs the error signals 22a and 22b. The outputs of the AND gates 516 and 517 enter at an OR gate 518 and the output of the OR gate 518 enters at the other input of the AND gate 519. The output of the AND gate 519 becomes a stop signal 59.
Now, consider forced termination of the test when all memories under test fails the test. If the test stop seizing signal 31a from the instruction memory 7 is xe2x80x9c1xe2x80x9d and the stop signal 31b is xe2x80x9c0xe2x80x9d, the signal 54a becomes xe2x80x9c1xe2x80x9d and the signal 54b becomes xe2x80x9c0xe2x80x9d in synchronization with the periodic clock signal 1. The output signal 56 of the status holding circuit 55 is thus asserted (=xe2x80x9c1xe2x80x9d) and the signal 58 obtained by delaying the signal 56 in the pipeline circuit 57 becomes xe2x80x9c1xe2x80x9d. Accordingly, if the signals 22 or 50 of all the memories under test are xe2x80x9c1xe2x80x9d, the stop signal 59 is asserted (=xe2x80x9c1xe2x80x9d) and terminates the test. The signal 59 serves as an operation inhibiting signal for the clock generator 6. If the signal 31a is xe2x80x9c0xe2x80x9d and the signal 31b is xe2x80x9c1xe2x80x9d, this stop function is disabled.
FIG. 38 is a flow chart showing a test flow of the erase test on the NOR type flash memories (simultaneous test on a plurality of memories under test); and FIG. 39 is a flow chart showing a write test flow under the same conditions. The flows of FIGS. 38 and 39 are obtained by adding the processing of the test apparatus (step S68 in FIG. 38 and step S84 in FIG. 39) to the aforementioned test flows of the prior art references (2) and (3).
Referring now to FIG. 38, a header address is set in step S60; a loop counter X of each DUT (Device (semiconductor memory) Under Test) is initialized to zero in step S61; and an erase mode such as erase time is set in step S62. Then, the loop counter of each DUT is incremented (X=X+1) in step S63; and an erase verification mode such as address and latency is set in step S64.
The next step S65 is to check the number of retries (1000 times) for each DUT. If the number of retries reaches to 1000, a xe2x80x9cfailxe2x80x9d DUT is excepted from the test in step S66. The clock of the xe2x80x9cfailxe2x80x9d DUT will be stopped until the end of the test, and the xe2x80x9cfailxe2x80x9d DUT is passed as a dummy without error reset. If the number of retries is less than 1000, whether the erasing has been completed or not is checked in step S67. If it has not been completed yet, the flow returns to step S62. The processing of steps S62 through S66 is repeated until the completion of the erasing. If the erasing has been completed, the flow goes to step S68.
In step S68, whether all the DUTs under test have passed the test or not is verified. If all of them have passed, the flow goes to step S70. If any one of them failed to pass, on the other hand, the clock of a xe2x80x9cpassxe2x80x9d DUT is temporarily stopped in step S69, and the flow returns to step S62. The processing of steps S62 through S69 is repeated until all the DUTs under test pass in step S68.
After excepting the xe2x80x9cfailxe2x80x9d DUT(s) from the test in step S70 as in step S66, whether all the DUTs have been excepted or not is verified in step S71. If all of them have been excepted, the processing is immediately terminated. If not, the temporary clock stop is canceled in step S72 and whether the present address is the last address or not is checked in step S73. If it is the last address, the processing is terminated. If not, the address is incremented in step S74 and the flow returns to step S64. This is the erase test flow.
Referring next to FIG. 39, a header address is set in step S80; a loop counter X of each DUT (Device (semiconductor memory) Under Test) is initialized to zero in step S81; a write mode is set in step S82; and write data, write address, and write time are set in step S83. Then, the loop counter of each DUT is incremented (X=X+1) in step S84; and a write verification mode such as latency is set in step S85.
The next step S86 is to check the number of retries (25 times) for each DUT. If the number of retries reaches to 25, the flow goes to step S87. If not, the flow goes to step S88. If all DUTs are judged as xe2x80x9cfailxe2x80x9d in step S87, the processing is immediately terminated. If not, the flow goes to step S91.
Step S88 is to check whether the writing has been completed or not. If it has not been completed yet, the flows returns to step S82 and repeats steps S82 through S86 until the writing is completed. If it has been completed, the flow goes to step S89.
In step S89, whether all the DUTs under test have passed or not is verified. If all of them have passed, the flow goes to step S92. If any one of them failed to pass, the clock of the xe2x80x9cpassxe2x80x9d DUT is temporarily stopped in step S90 and the flow returns to step S82. The processing of steps S82 through S90 is repeated until all the DUTs under test pass in step S89.
In step S91, the xe2x80x9cfailxe2x80x9d DUT is excepted from the test. The clock of the xe2x80x9cfailxe2x80x9d DUT will be stopped until the end of the test, and the xe2x80x9cfailxe2x80x9d DUT is passed as a dummy without error reset. The temporary clock stop is then canceled in step S92.
Next, whether the present address is the last address or not is checked in step S93. If it is the last address, the processing is terminated. If not, the address is incremented in step S94 and the flow returns to step S81.
Main circuits provided for the processing of each step in the above erase or write test flow are as follows: the address generator 10 for steps S60, S73, S74, S80, S93, S94; the register circuit 46 and the loop counter 47 for steps S61, S63, S65, S81, S84, S86; the control signal generator 16 for steps S62, S64, S82, S85; the data generator 14 for step S73; and the judging circuit 25, the clock stop latch circuit 43, and the error latch circuit 50 for the remaining steps.
 less than Problems with Flash Memory Test greater than 
In the NOR type flash memory, it is necessary to write xe2x80x9c0xe2x80x9d on all cells before erasing data in order to increase the threshold value. Otherwise, the threshold value of those memory cells becomes too low after the erase operation and the memory may fall into an unrecoverable excessive erase condition. Failure due to this excessive erasing has been one of the factors causing reduction in yield of the flash memory.
In the above mentioned erase test on the flash memory, it is also necessary to run a test while preventing in each erase operation excessive erasing of a cell (with a low threshold value) which has already been erased. This is because an already-erased memory cell and an yet-to-be-erased memory cell are mixed in a single memory under test during the erase retry operation since the speed of erasing each memory cell is different and because erasing of the flash memory is performed by one operation. The conventional flash memory, however, does not have a function to prevent excessive erasing of the already-erased memory cell(s). In addition, although the conventional test apparatus has an inhibiting function to temporarily stop the clock of the already-erased memory under test as shown in FIGS. 34 and 35 or 36 and 37, this function is to disable the entire memory under test so that a specific memory cell cannot be disabled.
 less than MGM Test greater than 
Concept of MGM
The MGM is a semiconductor memory which is provided with some error cells but regarded as acceptable since the number of normal cells is not less than a predetermined number. It is employed as a flash memory in a hard disk.
Hard disks have employed a sector method for data storage management, so that the flash memory to be applied needs to employ the same method for data management. FIG. 40 shows an internal structure of an AND type flash memory. In this memory, pass/fail information on each sector is written into a control region of the sector so that available sectors can be selected from that information. Thus, when the flash memory is the MGM, the numbers of good sectors and bad sectors are counted to check whether the number of good sectors is not less than a predetermined number or not.
 less than Problems with MGM Test greater than 
As means for the above mentioned test, the conventional semiconductor memory test apparatus fetches error information on each address into a failure bit memory device (built-in device or external device of the semiconductor memory test apparatus) during test. Then, after the test, it counts the number of errors by utilizing an analysis function of the failure bit memory device, generates error information on each memory under test, and combines that information with the error information therein.
In this case, the error information in the failure bit memory device is not immediately reflected during test on the semiconductor memory test apparatus. This results in an increase in overhead time of the MGM test.
A first aspect of the present invention is directed to a semiconductor test apparatus comprising: a control signal generating unit for supplying a control signal which indicates the execution of a predetermined operation to a semiconductor memory under test; a judging unit capable of making a pass/fail judgement on each address of the semiconductor memory under test after the execution of the predetermined operation; and an error information storage unit for sequentially giving a test address to the semiconductor memory under test and storing error address information including an error address which corresponds to the test address when an address is judged as xe2x80x9cfailxe2x80x9d by the judging unit, and error data outputted at that time.
According to a second aspect of the present invention, the semiconductor test apparatus according to the first aspect further comprises: an address generating unit for sequentially generating a generated address, wherein the error information storage unit includes: a test address selecting portion for selecting either the generated address or the error address as a test address given to the semiconductor memory under test.
According to a third aspect of the present invention, in the semiconductor test apparatus according to the second aspect, the semiconductor memory under test includes a plurality of semiconductor memories under test; the error address information contains total error information indicating the number of fetched error addresses, the error address information including a plural pieces of error address information corresponding to the plurality of semiconductor memories under test; and the error information storage unit includes a plurality of error information storage portions for storing the plural pieces of error address information, respectively, each of the plurality of error information storage portions having a total error information storage function of storing the total error information and a control signal output function of determining the end of the output of the test address on the basis of the total error information and generating a test operation stop signal indicating stop/nonstop of a test operation and a test content switching signal indicating switching of the contents of a test at the output of the test address. The semiconductor test apparatus further comprises: a test control unit for stopping a test on a semiconductor memory under test out of the plurality of semiconductor memories under test which corresponds to the test operation stop signal indicating stop of the test operation; and a test data generating unit for generating test data for the semiconductor memory under test on the basis of the indication contents of the test content switching signal.
According to a fourth aspect of the present invention, in the semiconductor test apparatus according to the second aspect, the semiconductor memory under test includes a plurality of semiconductor memories under test; the error address information contains total error information indicating the number of fetched error addresses, the error address information including a plural pieces of error address information corresponding to the plurality of semiconductor memories under test; and the error information storage unit includes a plurality of error information storage portions for storing the plural pieces of error address information, respectively, each of the plurality of error address storage portions having a control signal output function of generating a test operation stop signal indicating stop/nonstop of a test operation and a test content switching signal indicating switching of the contents of a test, at the output of the test address on the basis of a comparison result between the generated address and the error address. The semiconductor test apparatus further comprises: a test control unit for stopping a test on a semiconductor memory under test out of the plurality of memories under test which corresponds to the test operation stop signal indicating stop of the test operation; and a test data generating unit for generating test data for the semiconductor memory under test on the basis of the indication contents of the test content switching signal.
According to a fifth aspect of the present invention, the semiconductor test apparatus according to the first aspect further comprises: a first data generating unit for generating first data for each address, wherein the error information storage unit includes: a data arithmetic portion for processing the first data with the error data to obtain second data for test, for each error address; and a test data supplying portion for supplying either the first data or the second data to the semiconductor memory under test as test data.
According to a sixth aspect of the present invention, in the semiconductor test apparatus according to the fifth aspect, the error information storage unit further includes: a selection signal output portion for outputting a selection signal on the basis of a comparison result between the generated address and the error address, wherein the data arithmetic portion obtains the second data by an operation based on the selection signal.
According to a seventh aspect of the present invention, in the semiconductor test apparatus according to the first aspect, the semiconductor memory under test includes a plurality of semiconductor memories under test; the error address information contains total error information indicating the number of fetched error addresses, the error address information including a plural pieces of error address information corresponding to the plurality of semiconductor memories under test; and the error information storage unit includes a plurality of error information storage portions for storing the plural pieces of address information, respectively, each of the plurality of error information storage portions having a total error information storage function of storing the total error information and a forced control signal output function of receiving the total error information and error limit information defining the limited number of errors, and if the number of error addresses is not less than the limited number of errors, generating a test operation forced stop signal indicating forced stop of a test operation. The semiconductor test apparatus further compares: a test control unit for stopping tests on all of the plurality of semiconductor memories under test if the test operation forced stop signal indicates forced stop of the test operation.
An eighth aspect of the present invention is directed to a semiconductor test method for performing a test operation on a semiconductor memory under test by using the semiconductor test apparatus according to the first aspect. The semiconductor test method comprises the steps of: (a) setting an erase operation as the predetermined operation and performing an erase operation whereby to set all addresses of the semiconductor memory under test to xe2x80x9c1xe2x80x9d; and (b) immediately after the step (a), storing the error address information as to the semiconductor memory under test into the error information storage unit, whereas setting a write operation as the predetermined operation and performing a rewrite operation whereby to write a xe2x80x9c0xe2x80x9d to all addresses. If a write address is the error address in the rewrite operation, a xe2x80x9c0xe2x80x9d is exceptionally not written to an erase failure bit on the basis of the error data.
According to a ninth aspect of the present invention, in the semiconductor test method according to the eight aspect, the step (b) includes the steps of: (b-1) immediately after the step (a), storing the error address information as to the semiconductor memory under test into the error information storage unit; (b-2) setting a write operation as the predetermined operation and performing the rewrite operation on all addresses; and (b-3) immediately after the step (b-1), checking whether erasing of all addresses of the semiconductor memory under test has been normally completed or not, and terminating an erase test if it has been completed or performing the step (a) again if not. The first execution of the step (b-1) is performed on all addresses of the semiconductor memory under test; and the second and later executions of the step (b-1) are performed only on the error address indicated by the last error address information, out of all addresses of the semiconductor memory under test.
According to a tenth aspect of the present invention, in the semiconductor test method according to the ninth aspect, in the step (b-3), the erase test is also terminated if the number of times that erasing of all addresses of the semiconductor memory under test has not been normally completed exceeds a predetermined number of times.
According to an eleventh aspect of the present invention, in the semiconductor test method according to the tenth aspect, the semiconductor memory under test includes a plurality of semiconductor memories under test; the error address information contains total error information indicating the number of fetched error addresses, the error address information including a plural pieces of error address information corresponding to the plurality of semiconductor memories under test; and the steps (a) and (b) of the erase test are independently performed for each of the plurality of semiconductor memories under test. The semiconductor test method further comprises the step of: (c) making a pass/fail judgement on a corresponding semiconductor memory under test out of the plurality of semiconductor memories under test on the basis of the total error information, and if the corresponding semiconductor memory under test is judged as xe2x80x9cfailxe2x80x9d, forcefully stopping every processing of the erase tests on the plurality of semiconductor memories under test, the step (c) being performed after the erase test of the step (b-3) on each of the plurality of memories under test.
According to a twelfth aspect of the present invention, in the semiconductor test method according to the eighth aspect, the step (b) further includes the steps of: (b-1) obtaining a specified address; (b-2) determining if the specified address of the semiconductor memory under test agrees with the error address or not, and if it agrees with the error address, obtaining the error data from the error information storage unit; (b-3) setting a write operation as the predetermined operation and performing a rewrite operation whereby to write a xe2x80x9c0xe2x80x9d to the specified address, the steps (b-1) through (b-3) being repeated while the specified address is incremented, for each address; and (b-4) immediately after the repeating process of the steps (b-1) through (b-3) is completed, terminating the test if erasing of all addresses of the semiconductor memory under test has been normally completed or performing the step (a) again if not.
A thirteenth aspect of the present invention is directed to a semiconductor test method for performing a test operation on a semiconductor memory under test by using the semiconductor test apparatus according to the first aspect, wherein the error address information includes total error information indicating the number of fetched error addresses; and the semiconductor test apparatus further has a function of performing an error address information memory write operation whereby to write the error address to the semiconductor memory under test itself. The semiconductor test method comprises the steps of: (a) setting a write operation as the predetermined operation and performing a write operation whereby to write predetermined data to all addresses of the semiconductor memory under test; (b) immediately after the step (a), storing the error address information as to the semiconductor memory under test into the error information storage unit; and (c) making a pass/fail judgement on the semiconductor memory under test on the basis of the total error information, and if the memory is judged as xe2x80x9cpassxe2x80x9d, performing the error address information memory write operation.
In the semiconductor test apparatus of the first aspect, since the error information storage unit stores the error address information including the error address and the error data, the peculiar operation can be performed for each error address of the semiconductor memory under test on the basis of the error address information.
If the predetermined operation corresponds to a rewrite operation after the erase operation, for example, the peculiar rewrite operation can be performed for each error address of the semiconductor memory under test.
When a memory cell is allotted according to the number of bits of input/output data at the error address of the semiconductor memory under test, since the error address information includes the error data, the bits of the I/O data share the error address and which bit has an error can be accurately determined on the basis of the error data.
In the semiconductor test apparatus of the second aspect, the error information storage unit includes the test address selecting portion for selecting either the generated address or the error address as a test address given to the semiconductor memory under test. Accordingly, the predetermined operation can be performed only for the error address if necessary.
If the predetermined operation corresponds to a further erase operation after the erase and rewrite operations, the judging unit can make a pass/fail judgement only on the error address of the semiconductor memory under test found in the last erase operation.
In the semiconductor test apparatus of the third aspect, each of the plurality of error information storage portions has the total error information storage function of storing the total error information and the control signal output function of determining the end of the output of the test address on the basis of the total error information and generating the test operation stop signal indicating stop/nonstop of the test operation and the test content switching signal indicating switching of the contents of the test. The semiconductor test apparatus further comprises the test control unit for stopping the test on the semiconductor memory under test out of the plurality of semiconductor memories under test which corresponds to the test operation stop signal indicating stop of the test operation, and the test data generating unit for generating test data for the semiconductor memory under test on the basis of the indication contents of the test content switching signal.
Accordingly, for each of the plurality of memories under test, it is possible to suspend a test or to alter the contents of the test data depending on whether the output of the test address has been finished or not.
In the semiconductor test apparatus of the fourth aspect, each of the error information storage portions has the control signal output function of generating the test operation stop signal indicating stop/nonstop of the test operation and the test content switching signal indicating switching of the contents of the test, at the output of the test addresses on the basis of the comparison result between the generated address and the error address. The semiconductor test apparatus further comprises the test control unit for stopping the test on the semiconductor memory under test out of the plurality of memories under test which corresponds to the test operation stop signal indicating stop of the test operation, and the test data generating unit for generating test data for the semiconductor memory under test on the basis of the indication contents of the test content switching signal.
Accordingly, for each of the plurality of memories under test, it is possible to suspend the test or to alter the contents of the test data depending on the comparison result between the generated address and the error address.
In the semiconductor test apparatus of the fifth aspect, the test data supplying portion supplies either the first data produced in the first data generating portion or the second data obtained in the data arithmetic portion to the semiconductor memory under test as test data. For test, accordingly, various test data can be supplied to the semiconductor memory under test.
In the semiconductor test apparatus of the sixth aspect, the data arithmetic portion outputs the second data for test by performing an operation on the basis of the selection signal determined by the comparison result between the generated address and the error address. Thus, the second data for test varies according to the comparison result between the generated address and the error address.
In the semiconductor test apparatus, each of the plurality of error information storage portions has the total error information storage function of storing the total error information and the forced control signal output function of receiving the total error information and the error control information defining the limited number of errors, and if the number of error addresses is not less than the limited number of errors, generating the test operation forced stop signal indicating forced stop of the test operation. The semiconductor test apparatus further comprises the test control unit for stopping the tests on all of the plurality of semiconductor memories under test when the test operation forced stop signal indicates the forced stop of the test operation.
Accordingly, if the number of error addresses of any one of the plurality of memories under test exceeds the limited number of errors, the tests on all the semiconductor memories under test are forcefully terminated.
In the semiconductor test method of the eighth aspect, if a write address corresponds to the error address in the rewrite operation, a xe2x80x9c0xe2x80x9d is exceptionally not written to the erase failure bit on the basis of the error data while it is rewritten to the remaining bits. This surely prevents excessive erasing of the bit which has been normally erased while improving yield of the semiconductor memory under test.
In the semiconductor test method of the ninth aspect, the second and later executions of the step (b-1) are performed only on the error address indicated by the latest error address information out of all addresses of the semiconductor memory under test. That is, the addresses to be tested are narrowed down, which shortens the test time.
In the semiconductor test method of the tenth aspect, in the step (b-3), the erase test is also terminated if the number of times the erasing of all addresses of the semiconductor memory under test has not been normally completed exceeds a predetermined number of times. Accordingly, at the termination of the erase test, the semiconductor memory under test which includes the error address erased improperly can be recognized.
In the semiconductor test method of the eleventh aspect, the step (c) which is performed after the erase test of the step (b-3) for all the semiconductor memories under test is to make a pass/fail judgement on a corresponding semiconductor memory under test out of the plurality of semiconductor memories under test on the basis of the total error information. If the memory is judged as xe2x80x9cfailxe2x80x9d, the processing of the erase tests on all the semiconductor memories under test is forcefully terminated.
This speedy termination of the erase test on the other semiconductor memories under test allows effective conduct of the test, when the plurality of semiconductor memories under test become inoperable even with one error semiconductor memory under test.
In the semiconductor test method of the twelfth aspect, the error address judgment of the step (b-1) and the rewriting of the step (b-2) are repeated for each address while sequentially incrementing the specified address. Thus, the error information storage unit only has to store the error address information as to a single address. This simplifies the circuit configuration.
In the semiconductor test method of the thirteenth aspect, in the step (c), a pass/fail judgment on the semiconductor memory under test is made on the basis of the total error information, and if the memory is judged as xe2x80x9cpassxe2x80x9d, the error address information memory write operation is performed whereby to write the error address information to the semiconductor memory under test. This writing allows normal utilization of the semiconductor memory under test only with good addresses.
It is therefore an object of the present to provide semiconductor test apparatus which conducts a test on a nonvolatile semiconductor storage device such as a flash memory while preventing excessive erasing of data with reliability.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.